1. Field of the Invention
The present invention relates to a method for designing a wiring connecting section, in which wirings in mutually different wiring layers are electrically connected one another via a plurality of stack vias, and to a semiconductor device having a wiring connecting section designed by the method for designing a wiring connecting section.
2. Description of the Prior Art
In recent years, high integration of the semiconductor device has been further accelerated, and accompanied with such acceleration, also with regard to wirings of the semiconductor device, micro-fabrication and multi-layering have been promoted. In a semiconductor device having wiring layers of a multi-layered structure, vias (stack vias) are required for electrical connection through a plurality of wiring layers.
FIG. 1 is a plan view showing a wiring part of a conventional semiconductor device having wiring layers of a multi-layered structure, FIG. 2 is a longitudinal sectional view taken along a line I-I of FIG. 1, and FIG. 3 is a transverse sectional view taken along a line II-II of FIG. 2. Note that, in FIG. 2, illustration of an insulating layer and a semiconductor substrate below and under a wiring 51A is omitted.
FIG. 1 shows four wiring layers stacked on a semiconductor substrate 50 having specified elements (cells) formed thereon, with an insulating layer 60 interposed thereamong.
Here, the four wiring layers are referred to as a first wiring layer, a second wiring layer, a third wiring layer and a fourth wiring layer in order from a wiring layer closer to the semiconductor substrate 50. In the first and third wiring layers, wirings 51A and 53A running mainly in a horizontal direction (X direction) are formed, and in the second and fourth wiring layers, wirings 52A and 54A running mainly in a vertical direction (Y direction) are formed. Widths and wiring intervals of the wirings 51A, 52A, 53A and 54A are decided according to design rules.
Wirings in the different wiring layers are electrically connected via vias 61 penetrating through the insulating layer 60 provided among the wiring layers. A size of the vias 61 is also determined according to the design rules. Note that the vias 61 are divided into the ones for connecting wirings to each other and the ones for connecting the elements (cells) formed on the semiconductor substrate 50 and the wirings.
For example, in the case of two narrow-width wirings in mutually different wiring layers, these wirings are electrically connected via one via 61. However, in the case of connecting broad-width wirings such as the wirings 54A and 51A to each other, as shown in FIGS. 2 and 3, the vias 61 having a size determined by the design rules are arranged at an interval determined by the design rules over the entire portion where the wirings 54A and 51A cross with each other. Moreover, in the case of electrical connection through the plurality of wiring layers, as shown in FIGS. 2 and 3, pads 62 are provided over the entire region where the wirings 54A and 51A cross with each other in wiring layers (the second and third wiring layers) between the wiring 54A and 51A, and the vias 61 are arranged so as to be stacked in a vertical direction with the pads 62 interposed therebetween.
In general, the widths of the wirings and the wiring patterns of the respective wiring layers, the size, the positions and the number of the vias and the like are designed by a layout CAD (Computer-Aided Design) tool for a semiconductor device. Moreover, the design rules are determined by limitations on a fabrication process, electrical specifications required for the semiconductor device and the like. Vias stacked in the vertical direction as shown in FIG. 3 are referred to as stack vias.
The inventors of the present application conceive that problems to be described below are inherent in the conventional semiconductor device having the wiring connecting section of the above-described structure.
As described above, in the conventional semiconductor device, in the case of electrically connecting the broad-width wirings to each other, a large number of stack vias are uniformly arranged over the entire region where the wirings cross with each other. Accordingly, for example, in the case of connecting the broad-width wirings 51A of the first wiring layer and the broad-width wiring 54A of the fourth wiring layer, other wirings cannot be passed through the regions where the wirings 51A and 54A cross with each other as shown in FIG. 1, and it becomes necessary to arrange the other wirings so as to be detoured around the regions. In the example shown in FIG. 1, wirings shown with arrows are arranged so as to be detoured around the intersections (wiring connecting sections) of the wirings 51A and the wiring 54A since there exist the stack vias for connecting the wirings 51A and the wiring 54A.
As described above, in the conventional semiconductor device, it is necessary to arrange the other wirings so as to be detoured around the connecting regions of the broad-width wirings; therefore, the wirings are elongated, thus causing deterioration of the electrical characteristic and lowering a degree of freedom in designing the wirings. When the degree of freedom in designing the wiring is lowered, the number of wiring layers must be further increased, thus increasing a fabrication cost and lowering fabrication yield.